1. Technical Field
The present invention relates to a semiconductorprocessing defect monitor for diagnosing processing-induced defects.
2. Background Art
An ongoing concern in semiconductor technology, as well as any manufacturing technology, is the maximization of manufacturing yield. One phenomenon contributing to less than optimum manufacturing yields in semiconductor fabrication is that of processing-induced defects. These processing-induced defects cause within semiconductor circuits physical defects which, in turn, cause product failure. By way of example, these processing-induced defects have often been found to cause circuit failure due to open circuits in conductive lines, short-circuits between adjacent conductive lines, and short-circuits between overlying conductive lines at different planar levels. The causes of these processing defects are numerous, e.g., temperature variation, dust contamination in the work area, insufficient disposition of insulation layers, etc.
Analysis of processing-induced defects can be very useful in the prediction and improvement of manufacturing yield. It was found that the use of actual semiconductor products was not practical for the analysis of processing defects, because, in this era of Very Large Scale Integrated Circuits (VLSIC), a semiconductor device typically must undergo an extensive and complex testing procedure before it is found defective. Other than labeling the device as defective, this testing procedure typically yields little additional information as to the number of processing defects which have occurred, and, more important, yields little additional information as to where the defects can be located and visually inspected.
As a result of the above shortcomings, the trend in the semiconductor industry is to fabricate specialized semiconductor-processing defect monitors which have no use other than for the diagnosis of processing defects. Such defect monitor circuits are typically constructed separately from actual VLSIC devices and are discarded once useful defect information has been extracted from them. Typically, one of two approaches may be taken in utilizing these defect monitors.
A first manufacturing approach is periodically to process semiconductor wafers which are dedicated solely to the fabrication of defect monitors. These dedicated wafers are processed in the same processing environment as actual VLSIC devices (although at different times), and are then subjected to diagnosis to determine the defect density and the particular types of induced defects.
A second, more accurate manufacturing approach is the fabrication of defect monitors on the same wafers on which actual VLSIC devices are fabricated. The advantage of this approach is that the device monitors are fabricated in exactly the same processing environment and at exactly the same time as actual VLSIC devices. Thus, the processing defects induced on these defect monitors will be more accurately indicative of the processing defects induced in the actual products. In this approach, the defect monitors are typically fabricated within the kerf or discardable portion of the semiconductor wafer.
The design of a semiconductor-processing defect monitor can be varied in a number of ways to test for different failure types resulting from processing-induced defects.
As a first example, FIG. 1A shows a defect monitor having a simplified continuity-monitoring pattern. A line 6, which is shown connected to test contact pads 2 and 4, is made of a conductive material and is configured in a serpentine layout. After the fabrication this continuity-monitoring pattern by semiconductor-processing, electrical connections can be made to the test contact pads to test for continuity between the pads. If a processing variation has caused an open circuit defect along line 6, then an electrical discontinuity between the test contact pads will be indicated. In the design of the continuity-monitoring pattern of FIG. 1A, it should be noted that statistical calculations are often used to choose a length and width of line 6 such that there is a high probability of only one defect occurring along the line, thereby maintaining a one-to-one correspondence between the occurrence of a defect and the occurrence of a monitor failure so that the defect distribution density across a semiconductor wafer can be accurately determined. Finally, it should be noted that FIG. 1A is a simplified illustration of a continuity-monitoring pattern; i.e., a practical continuity-monitoring pattern would typically encompass a much greater length and complex serpentine structure, and would occupy a large area of a semiconductor layer.
As a second example, a defect monitor can also be designed to include a short-circuit monitoring pattern as shown in FIG. 1B. In FIG. 1B, test contact pads 10 and 14 are shown connected to bus bars 12 and 16, respectively, which in turn, are shown are connected to finger projections 11, 13, 15 and 17, 19, 21, respectively. These structures are all formed of a conductive material and are typically on the same planar level. In the construction of such a short-circuit monitoring pattern, the main objective is to test for processing-induced short-circuits between closely spaced parallel lines. If the processing variation has induced a short-circuit defect between two adjacent finger projections, the defect will be indicated by electrical continuity between the test contact pads 10 and 14. The space 18 represents a "minimum ground rule" spacing between adjacent finger projections 11 and 17. Similar minimum ground rule spacings are provided between the other adjacent finger projections. Statistical calculations can again be used to design an appropriate number of finger projections and to determine the minimum ground rule spacings, so that there is a high probability that only one process defect will occur per short-circuit monitoring pattern, thereby maintaining a one-to-one correspondence between the occurrence of a defect and the occurrence of a monitor failure to permit an accurate determination of the defect distribution density across the semiconductor wafer. Finally, it should also be noted that FIG. 1B is a simplified illustration of a short-circuit monitoring pattern; i.e., a practical short-circuit monitoring pattern would typically encompass a tremendous number of finger projections and would occupy a substantial semiconductor layout area.
As a third example, a semiconductor-processing defect monitor can also be constructed, as shown in FIG. 1C, to monitor for short-circuits between conductive lines on different planar levels. In Figure 1C, there is shown an upper conductive level 22 separated from a lower conductive level 20 by an insulating layer 24. The main object of such a defect monitor construction is to test for processing-induced short-circuits between overlying conductive levels. Typical insulating layer defects which can be induced during processing include localized thinning or absence of insulating material, porosity and/or pin holes in the insulating layer. If the processing variation induces a defect in the insulating layer 24 such that a short-circuit occurs, electrical continuity will be found to exist between the upper and lower conductive levels 22 and 20. Finally, it should again be noted that the defect monitor shown in FIG. 1C is a simplified illustration; i.e., a practical defect monitor would typically be much more complex to provide for testing for short-circuit occurrences between numerous planar levels.
The above semiconductor-procesing defect monitors are disclosed and further described in IBM Technical Disclosure Bulletin, Volume 17, No. 9, dated February 1975, and authored by Ghatalia and Thomas.
In addition, there are numerous other prior art references directed towards the construction and use of semiconductor-processing defect monitors.
For example, U.S. Pat. No. 3,983,479--Lee et al, assigned to the current assignee, discloses a defect monitor using a combination of continuity and short-circuit test patterns along with diode-mode FET amplifiers, such that testing can be made for defects without interference between adjacent patterns.
IBM Technical Disclosure Bulletin, Volume 20, No. 8, dated January 1978, and authored by Hallis, Levine and Scribner, discloses parallel serpentine test patterns having a first portion which is horizontally oriented, and a second portion which is vertically oriented, such that the defect monitor is sensitive to defects induced in the horizontal as well as the vertical direction.
IBM Technical Disclosure Bulletin, Volume 17, No. 12, dated May 1975, and authored by Cassani and Thomas, discloses a defect diagnostic circuit composed of an orthogonal array of metal lines and diffusion lines which can be diagnostically tested for various defects by selectively activating different transistors associated with each of said lines.
Additional references providing background for this technology include: U.S. Pat. No. 4,459,694-Ueno et al; U.S. Pat. No. 4,320,507-Fukushima et al; U.S. Patent No. 4,471,483-Chamberlain; U.S. Pat. No. 4,454,750-Tatematsu; U.S. Pat. No. 4,428,068-Baba; U.S. Pat. No. 4,061,908-de Jonge et al; U.S. Pat. No. 4,393,475-Kitagawa et al; U.S. Pat. No. 4,458,338-Giebel et al; U.S. Pat. No. 4,466,081-Masuoka; U.S. Pat. No. 4,468,759-Kung et al; Japanese Patent No. 97,334; and Japanese Patent No. 111,184.
The state of the semiconductor art is such that, if individual defects can be visually examined, diagnosis of the processing variation which caused the defect can be made to determine the appropriate corrective action. However, it should be stressed that, in order to facilitate this diagnosis, accurate location and visual observation of known defects are of key importance. As a further requirement, the location and visual observation operations should be readily and quickly implementable in order quickly to provide feedback data to prevent continued manufacturing under low yield processing conditions. Meeting these requirements is not an easy task, considering the fact that a typical processing-induced defect is of a submicron size, and can be located anywhere in a semiconductor circuit.
Although the defect monitors previously discussed typically produce good defect density data, these defect monitors usually produce little additional information as to where on the defect monitor circuit a particular defect has occurred. Instead, these testing approaches, simply utilizing continuity and/or conductivity measurements, produce only pass/fail data. Thus, if one of these defect monitors were found to be adversely affected by a processing defect, the entire defect monitor must be visually scanned with magnification instruments to locate and visually observed the defect. As test patterns typically occupy a substantial layout area of a semiconductor layer, it becomes a very tedious, or even impossible, task to use magnification instruments visually to scan the patterns for submicroscopic defects. Furthermore, as such visual scanning requires an exorbitant amount of time to produce diagnostic data, manufacturing yield is still negatively affected because of the substantial continued manufacting under low yield processing conditions.
Consequently, there has long existed a need for a semiconductor-processing defect monitor in which the location and visual observation of defects can be easily and readily implemented in order quickly to provide corrective feedback data.